1. Field of the Invention
The present invention relates to a technology for multiplexing and demultiplexing data between a high-speed line and a low-speed line using a reception buffer and a transmission buffer.
2. Description of the Related Art
Recently, a network mode that accommodates a large amount of data in a bulk structure on a high-speed line is increasingly used, while a backbone network of a low-speed line is still used.
Conventionally, data transfer is performed between the high-speed line and the low-speed line by multiplexing and demultiplexing the data. For example, Japanese Patent Application Laid-open No. H8-251128 discloses a technique in which a uniform clock synchronization is performed in a reception buffer of each of lines by selecting a normal line extracting clock from the lines and generating a reference clock in an apparatus. Japanese Patent Application Laid-open No. S58-094251 discloses a technique in which a frame phase synchronization is performed by generating an apparatus reference frame phase in a free-running state and absorbing a delay in a reception buffer of each of the lines.
However, according to the conventional techniques, a transmission delay (a delay of data transfer between the high-speed line and the low-speed line) cannot be reduced, and compensation of frame phase (compensation of frame phase with respect to the line having the bulk structure) cannot be performed.
In other words, in the technique disclosed in Japanese Patent Application Laid-open No. H8-251128, since the process timing of the reception buffer in the respective lines is only adjusted by synchronizing the clock, the transmission delay cannot be shortened, and the frame phase cannot be compensated.
In the technique disclosed in Japanese Patent Application Laid-open No. S58-094251, since the apparatus reference frame phase is generated in the free-running state to perform the frame phase synchronization, the frame phase cannot always be compensated, and the transmission delay cannot be shortened.